This relates to a power distribution network.
A conventional power distribution network may include an interposer mounted on a package substrate. Electrical and mechanical connections between the interposer and the package substrate are provided by a plurality of copper islands on a lower surface of the interposer, a copper island on an upper surface of substrate opposite the copper islands on the lower surface of the interposer, and solder balls or solder bumps connecting the copper islands on the interposer to the copper island on the substrate.
Through silicon vias (TSV) may extend through the interposer between the copper islands on the lower surface to contact pads on an upper surface of the interposer. Microvias (uVIA) may extend into the package substrate from the upper surface and connect to metal layers in the package substrate. These metal layers are connected by other microvias to still other metal layers or to a lower surface of the package substrate. The microvias and metal layers define electrical interconnection paths that connect the copper island on the upper surface of the package substrate to one or more surface connectors on the lower surface of the package substrate.
Unfortunately, this conventional power distribution network may have a high impedance peak and high Q factor which result in high power noise. The high power noise leads to undesirable high jitter at frequencies over 50 GigaHertz (GHz). The conventional power distribution network described above may also lead to high cost in terms of solder balls or bumps since there is a ball or bump for each power channel, lost space on the interposer and the package substrate that is used for the copper islands and/or lost area that is required for die capacitors.